The escalating demands for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as about 0.18 microns, increased transistor and circuit speeds, high reliability and increased production throughput with a low rejection rate for competitiveness in the market place. The reduction of design features to 0.25 microns and under generates numerous problems challenging the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric interlayer on a semiconductor substrate, such as doped monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer is deposited on the first dielectric layer. The metal layer is typically formed as a composite structure comprising sequentially deposited layers of titanium or tungsten, a primary conductive metal layer, such as aluminum or an aluminum alloy, and an upper anti-reflective coating, such as titanium nitride. A photoresist mask is then formed on the metal layer. The photoresist mask typically comprises a pattern of openings corresponding to various patterns consistent with circuit design. Such patterns typically include one or more dense arrays of metal features, such as conductive lines, spaced apart by gaps. Such a dense array of metal features is typically separated from an isolated metal feature or another dense array of metal features by a greater distance than the gap dimension separating the metal features within the particular dense array. For example, metal features in a dense array are typically spaced apart by a distance less than about 1 micron, e.g., about 0.375 microns for metal features of about 0.50 microns; whereas, an open field generally extends a distance greater than about 1 micron, such as greater than about 1.5 microns, e.g., greater than about 2 microns. A dielectric material, such as spin on glass (SOG), is typically deposited to fill in the gaps between the metal features, and baked at a temperature of about 300.degree. C. to about 450.degree. C. for a period of time up to about two hours, depending upon the particular SOG material employed. Planarization, as by chemical-mechanical polishing (CMP), is then performed.
Although semiconductor devices are being scaled in the horizontal direction, they are not generally scaled in the vertical dimension, since scaling in both dimensions would lead to a higher current density and that could exceed reliability limits. Horizontal scaling, therefore, requires conductive lines having a high aspect ratio, i.e., conductor height to conductive width of greater than 1, with reduced interwiring spacings. As a result, capacitive coupling between conductive lines becomes a primary limitation on circuit speed. If intrametal capacitance is high, the possibility for electric inefficiencies and inaccuracies increases. It is recognized that a reduction in capacitance within multi-level metallization systems will reduce the RC time constant between the conductive lines.
Various dielectric materials having a relatively low dielectric constant, e.g., a dielectric constant of less than about 4, have been proposed. One such dielectric material, hydrogen silsesquioxane (HSQ) offers many advantages for use in interconnect technology. HSQ is relatively carbon free, thereby rendering it unnecessary to etch back HSQ below the upper surface of the metal lines to avoid po-son via problems. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 microns employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200.degree. C. and it does not convert to the high dielectric constant glass phase until reaching temperatures of about 400.degree. C. in intermetal applications. As-deposited HSQ is considered a relatively low dielectric constant material with a dielectric constant of about 2.9-3.0, vis-a-vis silicon dioxide grown by thermal oxidation or chemical vapor deposition technique which has a dielectric constant of about 3.9-4.2. The mentioned dielectric constants are based on a scale wherein 1.0 represents the dielectric constant of air.
However, in attempting to employ various dielectric materials, particularly low dielectric constant materials such as HSQ, for gap filling, it was found that cracking typically occurs during subsequent thermal processing in fabricating the semiconductor device. Such subsequent thermal processing includes chemical vapor deposition of a planarizing oxide, such as a silicon dioxide derived from tetraethyl orthosilicate (TEOS) by plasma enhanced chemical vapor deposition (PECVD) or silicon dioxide derived from silane by PECVD. Gap fill dielectric cracking actually causes a deposited film to lift off of the metal features, thereby adversely impacting device reliability and increasing the rejection rate.
Accordingly, there exists a need for semiconductor methodology enabling the use of low dielectric constant dielectric materials, such as HSQ, for gap filling a patterned metal layer without cracking upon subsequent processing.